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use super::{InterruptKind, Priority, RunLevel};
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use crate::peripherals::INTERRUPT_CORE0;
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#[cfg(feature = "rt")]
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pub(super) fn init() {}
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pub(super) fn enable_cpu_interrupt_raw(cpu_interrupt: u32) {
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    INTERRUPT_CORE0::regs()
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        .cpu_int_enable()
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        .modify(|r, w| unsafe { w.bits((1 << cpu_interrupt) | r.bits()) });
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}
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pub(super) fn set_kind_raw(cpu_interrupt_number: u32, kind: InterruptKind) {
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    let interrupt_type = match kind {
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        InterruptKind::Level => 0,
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        InterruptKind::Edge => 1,
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    };
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    INTERRUPT_CORE0::regs()
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        .cpu_int_type()
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        .modify(|r, w| unsafe {
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            w.bits(
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                r.bits() & !(1 << cpu_interrupt_number) | (interrupt_type << cpu_interrupt_number),
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            )
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        });
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}
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pub(super) fn set_priority_raw(cpu_interrupt: u32, priority: Priority) {
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    INTERRUPT_CORE0::regs()
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        .cpu_int_pri(cpu_interrupt as usize)
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        .write(|w| unsafe { w.map().bits(priority as u8) });
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}
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pub(super) fn clear_raw(cpu_interrupt: u32) {
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    INTERRUPT_CORE0::regs()
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        .cpu_int_clear()
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        .write(|w| unsafe { w.bits(1 << cpu_interrupt) });
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}
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pub(super) fn cpu_interrupt_priority_raw(cpu_interrupt: u32) -> u8 {
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    INTERRUPT_CORE0::regs()
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        .cpu_int_pri(cpu_interrupt as usize)
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        .read()
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        .map()
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        .bits()
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}
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pub(super) fn current_runlevel() -> u8 {
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    INTERRUPT_CORE0::regs()
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        .cpu_int_thresh()
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        .read()
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        .bits()
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        .saturating_sub(1) as u8
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}
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pub(super) fn change_current_runlevel(level: RunLevel) -> u8 {
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    let prev_interrupt_priority = current_runlevel();
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    // The CPU responds to interrupts `>= level`, but we want to also disable
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    // interrupts at `level` so we set the threshold to `level + 1`.
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    INTERRUPT_CORE0::regs()
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        .cpu_int_thresh()
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        .write(|w| unsafe { w.bits(u32::from(level) + 1) });
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    prev_interrupt_priority
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}