use super::*;

use crate::{rtc_cntl::WakeLock, soc::clocks::ClockTree};

#[cfg_attr(i2c_master_version = "1", path = "v1.rs")]

#[cfg_attr(i2c_master_version = "2", path = "v2.rs")]

#[cfg_attr(

    any(i2c_master_version = "3", i2c_master_version = "4"),

    path = "v3.rs"

)]

mod version;

#[must_use = "futures do nothing unless you `.await` or poll them"]

pub(super) struct I2cFuture<'a> {

    events: EnumSet<Event>,

    driver: Driver<'a>,

    deadline: Option<Instant>,

    /// True if the Future has been polled to completion.

    finished: bool,

    _wake_lock: WakeLock,

}

impl<'a> I2cFuture<'a> {

        driver.regs().int_ena().modify(|_, w| {

                match event {

                    Event::EndDetect => w.end_detect().set_bit(),

                    Event::TxComplete => w.trans_complete().set_bit(),

                    #[cfg(i2c_master_has_tx_fifo_watermark)]

                    Event::TxFifoWatermark => w.txfifo_wm().set_bit(),

                };

            }

            w.arbitration_lost().set_bit();

            w.time_out().set_bit();

            w.nack().set_bit();

            #[cfg(i2c_master_has_fsm_timeouts)]

            {

                w.scl_main_st_to().set_bit();

                w.scl_st_to().set_bit();

            }

            w

        });

        Self::new_blocking(events, driver, deadline)

    pub fn new_blocking(

        events: EnumSet<Event>,

        driver: Driver<'a>,

        deadline: Option<Instant>,

    ) -> Self {

            events,

            driver,

            deadline,

            finished: false,

            _wake_lock: WakeLock::new(),

        }

    }

    fn is_done(&self) -> bool {

        !self.driver.info.interrupts().is_disjoint(self.events)

    }

        // Grab the current time before doing anything. This will ensure that a long

        // interruption still allows the peripheral sufficient time to complete the

        // operation (i.e. it ensures that the deadline is "at least", not "at most").

            Instant::now()

        } else {

            Instant::EPOCH

        };

        let error = self.driver.check_errors();

            // Even though we are done, we have to check for NACK and arbitration loss.

                // We are both done, and timed out. Likely the transaction has completed, but we

                // checked too late?

                Ok(())

            } else {

                error

            };

            Poll::Ready(result)

            Poll::Ready(error)

            && now > deadline

        {

            // If the deadline is reached, we return an error.

            Poll::Ready(Err(Error::Timeout))

        } else {

            Poll::Pending

        };

        if result.is_ready() {

        }

        result

}

impl core::future::Future for I2cFuture<'_> {

    type Output = Result<(), Error>;

            ctx.waker().wake_by_ref();

        }

        result

}

impl Drop for I2cFuture<'_> {

            }

        }

}

#[ram]

    // Disable all interrupts. The I2C Future will check events based on the

    // interrupt status bits.

    info.regs().int_ena().write(|w| unsafe { w.bits(0) });

}

/// Sets the filter with a supplied threshold in clock cycles for which a

/// pulse must be present to pass the filter.

fn set_filter(

    register_block: &RegisterBlock,

    sda_threshold: Option<u8>,

    scl_threshold: Option<u8>,

) {

    cfg_select! {

        i2c_master_separate_filter_config_registers => {

            register_block.sda_filter_cfg().modify(|_, w| {

                if let Some(threshold) = sda_threshold {

                    unsafe { w.sda_filter_thres().bits(threshold) };

                }

                w.sda_filter_en().bit(sda_threshold.is_some())

            });

            register_block.scl_filter_cfg().modify(|_, w| {

                if let Some(threshold) = scl_threshold {

                    unsafe { w.scl_filter_thres().bits(threshold) };

                }

                w.scl_filter_en().bit(scl_threshold.is_some())

            });

        }

        _ => {

            register_block.filter_cfg().modify(|_, w| {

                    unsafe { w.sda_filter_thres().bits(threshold) };

                }

                if let Some(threshold) = scl_threshold {

                    unsafe { w.scl_filter_thres().bits(threshold) };

                }

                w.sda_filter_en().bit(sda_threshold.is_some());

                w.scl_filter_en().bit(scl_threshold.is_some())

            });

        }

    }

}

#[expect(clippy::too_many_arguments)]

#[allow(unused)]

/// Configures the timing parameters for the I2C peripheral.

///

/// Clock source selection is handled separately via the clock tree.

fn configure_clock(

    info: &Info,

    scl_low_period: u32,

    scl_high_period: u32,

    scl_wait_high_period: u32,

    sda_hold_time: u32,

    sda_sample_time: u32,

    scl_rstart_setup_time: u32,

    scl_stop_setup_time: u32,

    scl_start_hold_time: u32,

    scl_stop_hold_time: u32,

    timeout: Option<u32>,

) -> Result<(), ConfigError> {

    unsafe {

        // scl period

        info.regs()

            .scl_low_period()

            .write(|w| w.scl_low_period().bits(scl_low_period as u16));

        #[cfg(not(i2c_master_version = "1"))]

        let scl_wait_high_period = scl_wait_high_period

            .try_into()

            .map_err(|_| ConfigError::FrequencyOutOfRange)?;

        info.regs().scl_high_period().write(|w| {

            #[cfg(not(i2c_master_version = "1"))] // ESP32 does not have a wait_high field

            w.scl_wait_high_period().bits(scl_wait_high_period);

            w.scl_high_period().bits(scl_high_period as u16)

        });

        // sda sample

        info.regs()

            .sda_hold()

            .write(|w| w.time().bits(sda_hold_time as u16));

        info.regs()

            .sda_sample()

            .write(|w| w.time().bits(sda_sample_time as u16));

        // setup

        info.regs()

            .scl_rstart_setup()

            .write(|w| w.time().bits(scl_rstart_setup_time as u16));

        info.regs()

            .scl_stop_setup()

            .write(|w| w.time().bits(scl_stop_setup_time as u16));

        // hold

        info.regs()

            .scl_start_hold()

            .write(|w| w.time().bits(scl_start_hold_time as u16));

        info.regs()

            .scl_stop_hold()

            .write(|w| w.time().bits(scl_stop_hold_time as u16));

        cfg_select! {

            i2c_master_has_bus_timeout_enable => {

                info.regs().to().write(|w| {

                    w.time_out_en().bit(timeout.is_some());

                });

            }

            _ => {

                info.regs()

                    .to()

                    .write(|w| w.time_out().bits(timeout.unwrap_or(1)));

            }

        }

    }

    Ok(())

}

/// Peripheral data describing a particular I2C instance.

#[doc(hidden)]

#[derive(Debug)]

#[non_exhaustive]

#[allow(private_interfaces, reason = "Unstable details")]

pub struct Info {

    /// Numeric instance id (0 = I2C0, 1 = I2C1, ...)

    #[cfg(soc_has_i2c1)]

    pub id: u8,

    /// Pointer to the register block for this I2C instance.

    ///

    /// Used with [`Self::register_block`] to access the register block.

    pub register_block: *const RegisterBlock,

    /// System peripheral marker.

    pub peripheral: crate::system::Peripheral,

    /// Interrupt handler for the asynchronous operations of this I2C instance.

    pub async_handler: InterruptHandler,

    /// SCL output signal.

    pub scl_output: OutputSignal,

    /// SCL input signal.

    pub scl_input: InputSignal,

    /// SDA output signal.

    pub sda_output: OutputSignal,

    /// SDA input signal.

    pub sda_input: InputSignal,

    /// I2C clock group instance.

    pub clock_instance: crate::soc::clocks::I2cInstance,

}

impl Info {

    /// Returns the register block for this I2C instance.

    pub fn regs(&self) -> &RegisterBlock {

    }

    /// Listens for the given interrupts.

    pub(super) fn enable_listen(&self, interrupts: EnumSet<Event>, enable: bool) {

        let reg_block = self.regs();

        reg_block.int_ena().modify(|_, w| {

            for interrupt in interrupts {

                match interrupt {

                    Event::EndDetect => w.end_detect().bit(enable),

                    Event::TxComplete => w.trans_complete().bit(enable),

                    #[cfg(i2c_master_has_tx_fifo_watermark)]

                    Event::TxFifoWatermark => w.txfifo_wm().bit(enable),

                };

            }

            w

        });

    }

    pub(super) fn interrupts(&self) -> EnumSet<Event> {

        let mut res = EnumSet::new();

        let reg_block = self.regs();

        let ints = reg_block.int_raw().read();

            res.insert(Event::EndDetect);

        }

            res.insert(Event::TxComplete);

        }

        #[cfg(i2c_master_has_tx_fifo_watermark)]

            res.insert(Event::TxFifoWatermark);

        }

        res

    }

    pub(super) fn clear_interrupts(&self, interrupts: EnumSet<Event>) {

        let reg_block = self.regs();

        reg_block.int_clr().write(|w| {

            for interrupt in interrupts {

                match interrupt {

                    Event::EndDetect => w.end_detect().clear_bit_by_one(),

                    Event::TxComplete => w.trans_complete().clear_bit_by_one(),

                    #[cfg(i2c_master_has_tx_fifo_watermark)]

                    Event::TxFifoWatermark => w.txfifo_wm().clear_bit_by_one(),

                };

            }

            w

        });

    }

}

impl PartialEq for Info {

    fn eq(&self, other: &Self) -> bool {

        core::ptr::eq(self.register_block, other.register_block)

    }

}

unsafe impl Sync for Info {}

pub(super) struct I2cClockGuard {

    clock: crate::clock::ll::I2cInstance,

}

impl I2cClockGuard {

        let clock = i2c.info().clock_instance;

        Self { clock }

}

impl Drop for I2cClockGuard {

}

#[derive(Clone, Copy)]

enum Deadline {

    None,

    Fixed(Instant),

    PerByte(Duration),

}

impl Deadline {

            Deadline::None => None,

            Deadline::Fixed(deadline) => Some(deadline),

        }

}

#[allow(dead_code)] // Some versions don't need `state`

#[derive(Clone, Copy)]

pub(super) struct Driver<'a> {

    pub(super) info: &'a Info,

    pub(super) state: &'a State,

    pub(super) config: &'a DriverConfig,

}

impl Driver<'_> {

    fn regs(&self) -> &RegisterBlock {

    }

        pin: crate::gpio::interconnect::OutputSignal<'_>,

        input: InputSignal,

        output: OutputSignal,

        guard: &mut PinGuard,

    ) {

        // avoid the pin going low during configuration

        pin.set_output_high(true);

        pin.apply_output_config(

            &OutputConfig::default()

                .with_drive_mode(DriveMode::OpenDrain)

                .with_pull(Pull::Up),

        );

        pin.set_output_enable(true);

        pin.set_input_enable(true);

        input.connect_to(&pin);

    fn init_master(&self, config: &Config) {

        self.regs().ctr().write(|w| {

            // Set I2C controller to master mode

            w.ms_mode().set_bit();

            w.sda_force_out().open_drain();

            w.scl_force_out().open_drain();

            // Use Most Significant Bit first for sending and receiving data

            w.tx_lsb_first().clear_bit();

            w.rx_lsb_first().clear_bit();

            w.sample_scl_level()

                .bit(config.scl_sample_level == Level::Low);

            #[cfg(i2c_master_has_arbitration_en)]

            w.arbitration_en().bit(config.bus_arbitration);

            #[cfg(i2c_master_version = "2")]

            w.ref_always_on().set_bit();

            // Ensure that clock is enabled

            w.clk_en().set_bit()

        });

    }

    /// Configures the I2C peripheral with the specified frequency, clocks, and

    /// optional timeout.

        // Configure filter

        // FIXME if we ever change this we need to adapt `set_frequency` for ESP32

        set_filter(self.regs(), Some(7), Some(7));

        // Configure frequency

        self.set_frequency(config)?;

        // Configure additional timeouts

        #[cfg(i2c_master_has_fsm_timeouts)]

        {

            self.regs()

                .scl_st_time_out()

                .write(|w| unsafe { w.scl_st_to().bits(config.scl_st_timeout.value()) });

            self.regs()

                .scl_main_st_time_out()

                .write(|w| unsafe { w.scl_main_st_to().bits(config.scl_main_st_timeout.value()) });

        }

        self.update_registers();

        Ok(())

        cfg_select! {

            i2c_master_has_reliable_fsm_reset => {

                // Device has a working FSM reset mechanism

                self.regs().ctr().modify(|_, w| w.fsm_rst().set_bit());

            }

            _ => {

                // Even though C2 and C3 have a FSM reset bit, esp-idf does not

                // define I2C_LL_SUPPORT_HW_FSM_RST for them, so include them in the fallback impl.

                // Restore configuration. This operation has succeeded once, so we can

                // assume that the config is valid and we can ignore the result.

            }

        }

    }

    /// Resets the I2C controller (FIFO + FSM + command list).

    // This function implements esp-idf's `s_i2c_hw_fsm_reset`

    // https://github.com/espressif/esp-idf/blob/27d68f57e6bdd3842cd263585c2c352698a9eda2/components/esp_driver_i2c/i2c_master.c#L115

    //

    // Make sure you don't call this function in the middle of a transaction. If the

    // first command in the command list is not a START, the hardware will hang

    // with no timeouts.

        } else {

        }

    }

    fn bus_busy(&self) -> bool {

        self.regs().sr().read().bus_busy().bit_is_set()

    fn ensure_idle_blocking(&self) {

            // If the bus is busy, we need to clear it.

        }

            // If the bus is busy, we need to clear it.

        }

    }

        // Clear all I2C interrupts

        // Reset fifo

        self.reset_fifo();

        // Reset the command list

        self.reset_command_list();

    /// Implements s_i2c_master_clear_bus.

    ///

    /// If a transaction ended incorrectly for some reason, the slave may drive SDA

    /// indefinitely. Forces the slave to release the bus by sending 9 clock pulses.

        let mut future = ClearBusFuture::new(*self, reset_fsm);

        let start = Instant::now();

                break;

            }

        }

            }

        })

    }

        cfg_select! {

            _ => self.force_pin_low(low, self.config.scl_pin.pin_number(), &self.info.scl_output),

        }

        cfg_select! {

            _ => self.force_pin_low(low, self.config.sda_pin.pin_number(), &self.info.sda_output),

        }

    /// Restores force_out to open-drain mode for both lines.

    #[cfg(i2c_master_has_pd_en)]

    fn restore_force_out(&self) {

        self.regs().ctr().modify(|_, w| {

            w.scl_force_out().open_drain();

            w.sda_force_out().open_drain()

        });

        self.update_registers();

    }

    #[cfg(not(i2c_master_has_pd_en))]

    fn force_pin_low(

        &self,

        low: bool,

        pin_number: Option<u8>,

        output_signal: &crate::gpio::OutputSignal,

    ) {

        use crate::gpio::AnyPin;

        let Some(n) = pin_number else { return };

        let pin = unsafe { AnyPin::steal(n) };

        if low {

            pin.set_output_high(false);

            output_signal.disconnect_from(&pin);

        } else {

            output_signal.connect_to(&pin);

        }

    }

    /// Sets or clears `scl_pd_en`. Switches `scl_force_out` to direct-output while

    /// pd_en is active (required on all chips), restoring OD mode when both pd_en

    /// bits clear.

    #[cfg(i2c_master_has_pd_en)]

    fn set_scl_pd(&self, low: bool) {

            self.regs()

                .ctr()

                .modify(|_, w| w.scl_force_out().direct_output());

        }

        self.regs()

            .scl_sp_conf()

            .modify(|_, w| w.scl_pd_en().bit(low));

            let sp = self.regs().scl_sp_conf().read();

                self.restore_force_out();

                return;

            }

        }

        self.update_registers();

    }

    /// Sets or clears `sda_pd_en`. Switches `sda_force_out` to direct-output while

    /// pd_en is active (required on all chips), restoring OD mode when both pd_en

    /// bits clear.

    #[cfg(i2c_master_has_pd_en)]

    fn set_sda_pd(&self, low: bool) {

            self.regs()

                .ctr()

                .modify(|_, w| w.sda_force_out().direct_output());

        }

        self.regs()

            .scl_sp_conf()

            .modify(|_, w| w.sda_pd_en().bit(low));

            let sp = self.regs().scl_sp_conf().read();

                self.restore_force_out();

                return;

            }

        }

        self.update_registers();

    }

    /// Resets the I2C peripheral's command registers.

    fn reset_command_list(&self) {

        for cmd in self.regs().comd_iter() {

            cmd.reset();

        }

    }

    /// Configures the I2C peripheral for a write operation.

    /// - `addr` is the address of the slave device.

    /// - `bytes` is the data to be sent

    /// - `start` indicates whether the operation should start by a START condition and sending the

    ///   address.

    /// - `stop` indicates whether the operation will end with a STOP condition.

    /// - `cmd_iterator` is an iterator over the command registers.

    fn setup_write<'a, I>(

        &self,

        addr: I2cAddress,

        bytes: &[u8],

        start: bool,

        stop: bool,

        cmd_iterator: &mut I,

    ) -> Result<(), Error>

    where

        I: Iterator<Item = &'a COMD>,

    {

        // If start is true we need to send the address, too, which takes up a data

        // byte.

            I2C_CHUNK_SIZE

        } else {

            I2C_CHUNK_SIZE + 1

        };

            return Err(Error::FifoExceeded);

        }

            add_cmd(cmd_iterator, Command::Start)?;

        }

        let write_len = if start { bytes.len() + 1 } else { bytes.len() };

        // don't issue write if there is no data to write

            // ESP32 can't alter the position of END, so we need to split the chunk always into

            // 3-command sequences. Chunking makes sure not to place a 1-byte

            // command at the end, which would cause an arithmetic underflow.

            // The sequences we can generate are:

            // - START-WRITE-STOP

            // - START-WRITE-END-WRITE-STOP

            // - START-WRITE-END-(WRITE-WRITE-END)*-WRITE-STOP sequence.

            if cfg!(i2c_master_version = "1") && !(start || stop) {

                // Chunks that do not have a START or STOP command need to be split into multiple

                // commands.

                add_cmd(

                    cmd_iterator,

                    Command::Write {

                        ack_exp: Ack::Ack,

                        ack_check_en: true,

                        length: (write_len as u8) - 1,

                    },

                )?;

                add_cmd(

                    cmd_iterator,

                    Command::Write {

                        ack_exp: Ack::Ack,

                        ack_check_en: true,

                        length: 1,

                    },

                )?;

            } else {

                add_cmd(

                    cmd_iterator,

                    Command::Write {

                        ack_exp: Ack::Ack,

                        ack_check_en: true,

                        length: write_len as u8,

                    },

                )?;

            }

        }

        if start {

            // Load address and R/W bit into FIFO

            match addr {

                I2cAddress::SevenBit(addr) => {

                    self.write_fifo((addr << 1) | OperationType::Write as u8);

                }

            }

        }

        for b in bytes {

        }

        Ok(())

    }

    /// Configures the I2C peripheral for a read operation.

    /// - `addr` is the address of the slave device.

    /// - `buffer` is the buffer to store the read data.

    /// - `start` indicates whether the operation should start by a START condition and sending the

    ///   address.

    /// - `stop` indicates whether the operation will end with a STOP condition.

    /// - `will_continue` indicates whether there is another read operation following this one and

    ///   the last byte must not be nacked.

    /// - `cmd_iterator` is an iterator over the command registers.

    fn setup_read<'a, I>(

        &self,

        addr: I2cAddress,

        buffer: &mut [u8],

        start: bool,

        stop: bool,

        will_continue: bool,

        cmd_iterator: &mut I,

    ) -> Result<(), Error>

    where

        I: Iterator<Item = &'a COMD>,

    {

            return Err(Error::ZeroLengthInvalid);

        }

            (I2C_CHUNK_SIZE + 1, buffer.len())

        } else {

            (I2C_CHUNK_SIZE, buffer.len() - 1)

        };

            return Err(Error::FifoExceeded);

        }

            add_cmd(cmd_iterator, Command::Start)?;

            // WRITE 7-bit address

            add_cmd(

                cmd_iterator,

                Command::Write {

                    ack_exp: Ack::Ack,

                    ack_check_en: true,

                    length: 1,

                },

            )?;

        }

            let extra_commands = if cfg!(i2c_master_version = "1") {

                match (start, will_continue) {

                    // No chunking (START-WRITE-READ-STOP) or first chunk (START-WRITE-READ-END)

                    (true, _) => 0,

                    // Middle chunk - (READ-READ-READ-END)

                    (false, true) => 2,

                    // Last chunk - (READ-READ-STOP-END)

                    (false, false) => 1 - stop as u8,

                }

            } else {

                0

            };

            add_cmd(

                cmd_iterator,

                Command::Read {

                    ack_value: Ack::Ack,

                    length: initial_len as u8 - extra_commands,

                },

            )?;

            for _ in 0..extra_commands {

                add_cmd(

                    cmd_iterator,

                    Command::Read {

                        ack_value: Ack::Ack,

                        length: 1,

                    },

                )?;

            }

        }

        if !will_continue {

            // this is the last read so we need to nack the last byte

            // READ w/o ACK

            add_cmd(

                cmd_iterator,

                Command::Read {

                    ack_value: Ack::Nack,

                    length: 1,

                },

            )?;

        }

        self.update_registers();

            // Load address and R/W bit into FIFO

            match addr {

                I2cAddress::SevenBit(addr) => {

                }

            }

        }

        Ok(())

    }

    /// Reads from RX FIFO into the given buffer.

            return Err(Error::ExecutionIncomplete);

        }

        // Read bytes from FIFO

        for byte in buffer.iter_mut() {

        }

        // The RX FIFO should be empty now. If it is not, it means we queued up reading

        // more data than we read, which is an error.

        Ok(())

    /// Clears all pending interrupts for the I2C peripheral.

    fn clear_all_interrupts(&self) {

        self.regs()

            .int_clr()

            .write(|w| unsafe { w.bits(property!("i2c_master.ll_intr_mask")) });

    }

    }

    /// Waits for the completion of an I2C transaction.

        let mut future =

            I2cFuture::new_blocking(Event::TxComplete | Event::EndDetect, *self, deadline);

        loop {

                result?;

                return self.check_all_commands_done_blocking(deadline);

            }

        }

        // NOTE: on esp32 executing the end command generates the end_detect interrupt

        //       but does not seem to clear the done bit! So we don't check the done

        //       status of an end command

            Instant::now()

        } else {

            Instant::EPOCH

        };

        self.check_errors()?;

        for cmd_reg in self.regs().comd_iter() {

            let cmd = cmd_reg.read();

            // if there is a valid command which is not END, check if it's marked as done

                // Let's retry

                    && now > deadline

                {

                    return Err(Error::ExecutionIncomplete);

                }

                return Ok(false);

            }

            // once we hit END or STOP we can break the loop

                break;

            }

            if cmd.opcode().is_stop() {

                #[cfg(i2c_master_version = "1")]

                // wait for STOP - apparently on ESP32 we otherwise miss the ACK error for an

                // empty write

                if self.regs().sr().read().scl_state_last() == 6 {

                    self.check_errors()?;

                } else {

                    continue;

                }

                break;

            }

        }

        Ok(true)

    /// Returns whether all I2C commands have completed execution.

    fn check_all_commands_done_blocking(&self, deadline: Option<Instant>) -> Result<(), Error> {

        // loop until commands are actually done

        self.check_errors()?;

        Ok(())

    }

    /// Returns whether all I2C commands have completed execution.

        // loop until commands are actually done

        }

        Ok(())

    /// Checks for I2C transmission errors and handles them.

    ///

    /// Inspects specific I2C-related interrupts to detect errors during

    /// communication, such as timeouts, failed acknowledgments, or arbitration loss.

    /// If an error is detected, resets the I2C peripheral to clear the error condition

    /// and returns an appropriate error.

        let r = self.regs().int_raw().read();

        // Handle error cases

            return Err(Error::AcknowledgeCheckFailed(estimate_ack_failed_reason(

                self.regs(),

            )));

        }

            return Err(Error::ArbitrationLost);

        }

        #[cfg(not(i2c_master_version = "1"))]

            return Err(Error::AcknowledgeCheckFailed(

                AcknowledgeCheckFailedReason::Data,

            ));

        }

        #[cfg(i2c_master_has_fsm_timeouts)]

        {

                return Err(Error::Timeout);

            }

            if r.scl_main_st_to().bit_is_set() {

                return Err(Error::Timeout);

            }

        }

        if r.time_out().bit_is_set() {

            return Err(Error::Timeout);

        }

        Ok(())

    /// Updates the configuration of the I2C peripheral.

    ///

    /// Ensures that configuration values, such as clock settings, SDA/SCL filtering,

    /// timeouts, and other operational parameters configured in other methods, are

    /// propagated to the I2C hardware. This step synchronizes the software-configured

    /// settings with the peripheral's internal registers.

    fn update_registers(&self) {

        // Ensure that the configuration of the peripheral is correctly propagated

        // (only necessary for C2, C3, C6, H2 and S3 variant)

        #[cfg(i2c_master_has_conf_update)]

        self.regs().ctr().modify(|_, w| w.conf_upgate().set_bit());

    }

    fn set_frequency(&self, config: &Config) -> Result<(), ConfigError> {

        version::set_frequency(self, config)

    }

    fn reset_fifo(&self) {

        version::reset_fifo(self);

    }

    fn read_fifo(&self) -> u8 {

        version::read_fifo(self.regs())

    }

    fn write_fifo(&self, data: u8) {

        version::write_fifo(self.regs(), data);

    }

    /// Starts an I2C transmission.

    fn start_transmission(&self) {

        // Start transmission

        self.regs().ctr().modify(|_, w| w.trans_start().set_bit());

    }

        &self,

        address: I2cAddress,

        buffer: &[u8],

        start: bool,

        stop: bool,

        deadline: Deadline,

    ) -> Result<Option<Instant>, Error> {

        let cmd_iterator = &mut self.regs().comd_iter();

        self.setup_write(address, buffer, start, stop, cmd_iterator)?;

            add_cmd(cmd_iterator, Command::Stop)?;

        }

            // Multi-chunk write, terminate with END. ESP32 TRM suggests a write should work with

            // only a STOP at the end, but STOP does not seem to generate a TX_COMPLETE interrupt

            // without END.

            add_cmd(cmd_iterator, Command::End)?;

        }

        self.start_transmission();

    /// Executes an I2C read operation.

    /// - `addr` is the address of the slave device.

    /// - `buffer` is the buffer to store the read data.

    /// - `start` indicates whether the operation should start by a START condition and sending the

    ///   address.

    /// - `stop` indicates whether the operation should end with a STOP condition.

    /// - `will_continue` indicates whether there is another read operation following this one and

    ///   the last byte must not be nacked.

    /// - `cmd_iterator` is an iterator over the command registers.

        &self,

        address: I2cAddress,

        buffer: &mut [u8],

        start: bool,

        will_continue: bool,

        stop: bool,

        deadline: Deadline,

    ) -> Result<Option<Instant>, Error> {

        // We don't support single I2C reads larger than the FIFO. This should be

        // enforced by `VariableChunkIterMut` used in `Driver::read` and

        // `Driver::read_async`.

        let cmd_iterator = &mut self.regs().comd_iter();

        self.setup_read(address, buffer, start, stop, will_continue, cmd_iterator)?;

            add_cmd(cmd_iterator, Command::Stop)?;

        }

            // Multi-chunk read, terminate with END. On ESP32, assume same limitation as writes.

            add_cmd(cmd_iterator, Command::End)?;

        }

        self.start_transmission();

    /// Executes an I2C write operation.

    /// - `addr` is the address of the slave device.

    /// - `bytes` is the data to be sent

    /// - `start` indicates whether the operation should start by a START condition and sending the

    ///   address.

    /// - `stop` indicates whether the operation should end with a STOP condition.

    /// - `cmd_iterator` is an iterator over the command registers.

    fn write_operation_blocking(

        &self,

        address: I2cAddress,

        bytes: &[u8],

        start: bool,

        stop: bool,

        deadline: Deadline,

    ) -> Result<(), Error> {

        address.validate()?;

        // Short circuit for zero length writes without start or end as that would be an

        // invalid operation write lengths in the TRM (at least for ESP32-S3) are 1-255

            return Ok(());

        }

        Ok(())

    }

    /// Executes an I2C read operation.

    /// - `addr` is the address of the slave device.

    /// - `buffer` is the buffer to store the read data.

    /// - `start` indicates whether the operation should start by a START condition and sending the

    ///   address.

    /// - `stop` indicates whether the operation should end with a STOP condition.

    /// - `will_continue` indicates whether there is another read operation following this one and

    ///   the last byte must not be nacked.

    /// - `cmd_iterator` is an iterator over the command registers.

    fn read_operation_blocking(

        &self,

        address: I2cAddress,

        buffer: &mut [u8],

        start: bool,

        stop: bool,

        will_continue: bool,

        deadline: Deadline,

    ) -> Result<(), Error> {

        address.validate()?;

        // Short circuit for zero length reads as that would be an invalid operation

        // read lengths in the TRM (at least for ESP32-S3) are 1-255

        if buffer.is_empty() {

            return Ok(());

        }

        let deadline =

        self.read_all_from_fifo(buffer)?;

        Ok(())

    }

    /// Executes an async I2C write operation.

    /// - `addr` is the address of the slave device.

    /// - `bytes` is the data to be sent

    /// - `start` indicates whether the operation should start by a START condition and sending the

    ///   address.

    /// - `stop` indicates whether the operation should end with a STOP condition.

    /// - `cmd_iterator` is an iterator over the command registers.

    async fn write_operation(

        bytes: &[u8],

        start: bool,

        stop: bool,

        deadline: Deadline,

        // Short circuit for zero length writes without start or end as that would be an

        // invalid operation write lengths in the TRM (at least for ESP32-S3) are 1-255

            return Ok(());

        }

        Ok(())

    /// Executes an async I2C read operation.

    /// - `addr` is the address of the slave device.

    /// - `buffer` is the buffer to store the read data.

    /// - `start` indicates whether the operation should start by a START condition and sending the

    ///   address.

    /// - `stop` indicates whether the operation should end with a STOP condition.

    /// - `will_continue` indicates whether there is another read operation following this one and

    ///   the last byte must not be nacked.

    /// - `cmd_iterator` is an iterator over the command registers.

    async fn read_operation(

        start: bool,

        stop: bool,

        will_continue: bool,

        // Short circuit for zero length reads as that would be an invalid operation

        // read lengths in the TRM (at least for ESP32-S3) are 1-255

            return Ok(());

        }

        let deadline =

        Ok(())

        &self,

        address: I2cAddress,

        buffer: &mut [u8],

        start: bool,

        stop: bool,

        will_continue: bool,

        deadline: Deadline,

    ) -> Result<(), Error> {

        let chunk_count = VariableChunkIterMut::new(buffer).count();

        for (idx, chunk) in VariableChunkIterMut::new(buffer).enumerate() {

            self.read_operation_blocking(

                address,

                chunk,

                start && idx == 0,

                deadline,

            )?;

        }

        Ok(())

        &self,

        address: I2cAddress,

        buffer: &[u8],

        start: bool,

        stop: bool,

        deadline: Deadline,

    ) -> Result<(), Error> {

            return self.write_operation_blocking(address, &[], start, stop, deadline);

        }

        let chunk_count = VariableChunkIter::new(buffer).count();

        for (idx, chunk) in VariableChunkIter::new(buffer).enumerate() {

            self.write_operation_blocking(

                address,

                chunk,

                deadline,

            )?;

        }

        Ok(())

    async fn read(

        stop: bool,

                chunk,

            )

        }

        Ok(())

    async fn write(

                .write_operation(address, &[], start, stop, deadline)

        }